Read only memory (ROM) and programmable logic array (PLA) integrated circuits are widely used in data processing systems. ROM and PLA integrated circuits typically store fixed information in binary form using electronic switching devices. The personalization of binary information is generally carried out by forming electronic devices which are either electrically conductive or electrically nonconductive. Each of these alternate states is established during the device's fabrication.
In state of the art Metal Oxide Silicon Field Effect Transistor (MOSFET) technologies, the personalization of the Field Effect Transistor (FET) is commonly done at the device gate level. Since the MOSFET's threshold voltage is directly proportional to the thickness of the gate insulator, an FET device with a gate insulator thickness equivalent to the thickness of the isolating field insulator, will be nonconducting when normal operating voltages are applied to the device. Such a device will constitute a first binary state. Those FET devices with a relatively thinner gate insulating layer, will be electrically conductive under the same operating voltages, and they will constitute a second binary state. U.S. Pat. No. 3,541,543 describes this technique for fabricating read only memory FET devices.
The personalization of the permanently stored binary state of read only memory or PLA FET devices is conventionally carried out by forming thick or thin gate insulator regions using photolithographic masking. For example, in selfaligned recessed oxide polycrystalline silicon gate MOSFET technologies, the thin gate insulator region is defined in the process. This method of read only memory personalization has the disadvantage that it requires a long turnaround time before a particular pattern of binary bits can be embodied in a final read only memory product. As a result, the development times for systems employing conventional FET read only memories is relatively long and engineering changes considerably lengthen the development cycle time for a product.
In order to reduce the turnaround time necessary to obtain a useable product incorporating a read only memory, an alternate method of ROM or PLA personalization is conventionally used which employs the ion implantation of semiconductor dopant ions to selectively change the conduction threshold voltage of the resultant FET device. An example of this technique is described in U.S. Pat. No. 4,142,176, wherein the personalization takes place after the thin gate insulating layer has been grown. However, even though the processing time for devices made in accordance with this process is reduced when compared with earlier methods, the overall turnaround time is still long.
Still another approach to reducing the overall turnaround time for fabricating ROM or PLA products with predefined permanent bit patterns, is to use metal interconnection line personalization. In this approach, the metal interconnection lines which are employed to interconnect the various devices on the integrated circuit chip, are established at a later time during the process cycle. In ROM and PLA products, a device which is intended to be an electrically conductive device, has its gate electrode connected to the word line by means of a metal interconnection line. Those devices which are not designated as conductive devices, do not have their gate electrodes so connected, but instead can have their gate electrode shorted to their source. The turnaround time necessary to obtain a finished product employing this method is reduced with respect to the previously described processes, however, since an additional gate electrode contact is required for each storage cell, the cell size increases significantly, thereby reducing the overall density of the ROM or PLA product.
A still further improved solution to reducing the overall turnaround time problem is to employ Electrically Erasable Programmable Read Only Memories (EEPROM). In this approach, the ROM or PLA device personality can be electrically changed over a period of several minutes to hours. An example of EEPROM cells is found in U.S. Pat. No. 4,334,292 to Koetcha. The EEPROM cells typically incorporate capacitors and therefore the cell size becomes relatively large, thereby reducing the overall density of the resultant memory product.
What is required is a practical technique for fabricating ROM and PLA products which has a superior turnaround time and yet results in a product having a high information density.
It is of further importance to provide FET devices which have a high switching speed in order to maximize the performance of the resultant ROM or PLA product. An example FET device structure which realizes such high performance characteristics is described in the publication Ogura, et al, "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field Effect Transistor", IEEE Transactions On Electron Devices, August, 1980, pages 1359-1367. The LDD field effect transistor structure has reduced short channel effects by virtue of having a relatively lightly doped source and drain extensions adjacent to the gate region. This enables higher current driving characteristics for the resultant FET device with a lowered gate capacitance.
A further benefit in such device structures is the reduction in hot electron effects as described in Ogura, et al., "Elimination of Hot Electron Gate Current by the Lightly Doped Drain-Source Structure," IEDM-81, pages 651-654. In this reference, Ogura, et al. have an initial ion implantation step to form the lightly doped portions of source and drain adjacent to the edges of the gate, followed by the growth of silicon dioxide sidewalls which will serve as masks to limit the area of subsequent deep ion implantation to regions separated from the gate.
It would be desirable to have a process which could selectively provide Lightly Doped Drain (LDD) field effect transistor devices in those locations of a read only memory or PLA product, requiring devices having a conductive state and alternately to provide nonconductive FET devices in those locations of the ROM or PLA product which are desired to have a nonconductive state. A simplified fabrication process which would provide a pattern of selectively conductive and nonconductive LDD field effect transistor devices, which can be selectively personalized for their respective binary states at a relatively late stage in the fabrication process, would result in a high density read only memory or PLA product having a desirably fast turnaround time with a resultant conductive FET devices having high performance characteristics.